The present invention relates to a semiconductor device.
In the field of electric power converters using a semiconductor device, matrix converters have been known to the persons skilled in the art as direct converter circuits which conduct an alternating current to alternating current conversion (hereinafter referred to an “AC/AC conversion”), an alternating current to direct current conversion (hereinafter referred to an “AC/DC conversion”) and a direct current to alternating current conversion (hereinafter referred to a “DC/AC conversion”) without employing any DC smoothing circuit including an electrolytic capacitor and a DC reactor.
The matrix converter includes AC switches. Since an AC voltage is applied to the AC switches, it is required for the AC switches to exhibit withstand voltages in the forward and reverse directions. In other words, the AC switches are required to exhibit a forward withstand voltage and a reverse withstand voltage. From the view points of reducing the size, weight and costs of the matrix converter and improving the conversion efficiency and response speed thereof, bidirectional switching apparatuses have been attracting much attention. As one of the bidirectional switching apparatuses, a switch including two reverse blocking insulated gate bipolar transistors (hereinafter referred to as “reverse blocking IGBT's”) connected in parallel to each other has been known to the persons skilled in the art.
In the following descriptions and the accompanying drawings, electrons or holes are the majority carries in the layers and regions prefixed with “n-type” or “p-type”. The sign − on the shoulder of the letter “n” or “p” indicating the conductivity type of a region or a layer indicates that the region or the layer is doped relatively lightly. The sign + on the shoulder of the letter “n” or “p” indicating the conductivity type of a region or a layer indicates that the region or the layer is doped relatively heavily. When neither the sign + nor the sign − is fixed, the region or the layer is doped intermediately.
FIG. 11 is the cross sectional view of a conventional reverse blocking IGBT.
Referring now to FIG. 11, separation section 130 that surrounds active region 110 is formed in the edge area of an n-type semiconductor substrate in the reverse blocking IGBT. In active region 110, a vertical IGBT, including n−-type drift region 1, p-type base region 2, n+-type emitter region 3, and p-type collector region 10, is formed. In separation section 130, p-type separation region 31 is formed through the semiconductor substrate from the front surface thereof to the back surface thereof. Separation region 31 is in contact with collector region 10 formed on the active region 110 back surface. Between separation section 130 and active region 110, breakdown withstanding region 120 is formed. Breakdown withstanding region 120 relaxes the electric field strength on the pn-junction constituting the semiconductor device and realizes the desired withstand voltages.
FIG. 12 is a cross sectional view showing active region 110 in the semiconductor device shown in FIG. 11 in detail.
In active region 110, p-type base region 2 is formed selectively in the surface portion on the front side of drift region 1 formed of an n−-type semiconductor substrate. Base region 2 is doped more heavily than drift region 1. In the base region 2 surface portion, n+-type emitter region 3 and p+-type body region 4 are formed selectively. Gate electrode 7 covers a part of n+-type emitter region 3 and a part of base region 2 via gate insulator film 6. Emitter electrode 9 is in contact with emitter region 3 and body region 4. Emitter electrode 9 is insulated from gate electrode 7 by interlayer insulator film 8. On the drift region 1 back surface, p-type collector region 10 and collector electrode 11 are formed.
By employing a silicon (Si) substrate fabricated by the floating zone method (hereinafter referred to as the “FZ method”), the reverse blocking IGBT as described above is formed to be a non-punch-through-type (hereinafter referred to as an “NPT-type”) one, in which the depletion layer expanding from the emitter in the OFF-state of the reverse blocking IGBT does not reach the collector. Due to the technical improvement for polishing the silicon substrate fabricated by the FZ method, it is possible to thin the silicon substrate to be around 100 μm in thickness at the IGBT rated voltage of 600 V and to be around 180 μm in thickness at the IGBT rated voltage of 1200 V. By thinning the collector region and by lowering the impurity concentration in the collector region, the NPT-type IGBT is provided with a structure that lowers the injection efficiency of the minority carriers and raises the transport efficiency thereof. By forming the reverse blocking IGBT to be an NPT-type one, the problems caused by the tradeoff relation between the ON-voltage characteristics and the turnoff loss are obviated and both the ON-voltage and the turnoff loss are reduced.
The following Patent Document 1 proposes a semiconductor device as the reverse blocking IGBT as described above. The proposed semiconductor device includes a semiconductor substrate; a p-type base region in the surface portion of the semiconductor substrate; an n+ emitter region in the surface portion of the p-type base region; a p+ collector region in the edge area of the semiconductor substrate and on the back surface side of the semiconductor substrate, the p+ collector region surrounding the p-type base region. In other words, a p+ region is on the side face of the semiconductor substrate and a p+ collector region is on the back surface side of the semiconductor substrate. The p+ collector region on the back surface side of the semiconductor substrate is around 1 μm in thickness.
The following Patent Document 2 proposes a high-voltage semiconductor device as described below that exhibits high forward and reverse withstand voltages. The high-voltage semiconductor device proposed in the following Patent Document 2 includes a semiconductor substrate including a drift layer, on both side of which pn-junctions for forward and reverse breakdown withstanding are formed, and a separation diffusion region working for the breakdown-withstanding junction edge-termination structure for the pn-junctions, the separation diffusion region being formed from the first major surface side of the semiconductor substrate. The drift layer includes a region, the impurity concentration distribution therein is substantially constant inward from the first major surface side or the impurity concentration therein reduces inward from the first major surface side.
FIG. 13(a) is the cross sectional view of another conventional reverse blocking IGBT.
The conventional reverse blocking IGBT shown in FIG. 13(a) includes n-type shell region 201 between drift region 1 and base region 2. Shell region 201 is doped more heavily than drift region 1. Between drift region 1 and collector region 10, n-type buffer region 202 is formed. Buffer region 202 is doped more heavily than drift region 1. The other structures are the same with the structures in the reverse blocking IGBT shown in FIG. 11.
The IGBT's having the structures as described below for improving the performances thereof are known to the persons skilled in the art.
The IGBT that includes a region, the conductivity type of which is the same with the conductivity type of the drift region. The region is doped more heavily than the drift region and disposed between the drift region and the base region or between the drift region and the collector region.
The IGBT that includes regions, the conductivity type of which is the same with the conductivity type of the drift region. The regions are doped more heavily than the drift region. One of the regions is disposed between the drift region and the base region. The other one of the regions is disposed between the drift region and the collector region.
The following Patent Document 3 proposes a semiconductor device as one of the IGBT's described above. The IGBT proposed in the Patent Document 3 includes four doped regions, the conductivity types of which are different from one another alternately. The doped regions are laid one on another. The dimensions of one of the doped regions (first base region) are determined with respect to punch-through. The proposed IGBT includes also two buffer layers. The conductivity type of the buffer layers is the same with the conductivity type of the first base region and the buffer layers are doped more heavily than the first base region for interrupting the IGBT symmetrically. The forward and reverse withstand voltages of the proposed IGBT are set to be almost the same.
The following Patent Document 4 proposes another semiconductor device (IGBT) as described below. The IGBT proposed in the Patent Document 4 includes a heavily doped region at least in a part of the boundary between a p-type base region and an n-type drift region. The conductivity type of the heavily doped region is the same with the conductivity type of the n-type drift region. The heavily doped region is doped more heavily than the n-type drift region. The structure described above shortens the channel length and reduces the voltage drop in the ON-state of the device.
The following Patent Document 5 proposes still another semiconductor device (IGBT) as described below. The IGBT proposed in the Patent Document 5 includes a short-lifetime region in the portion of an n-type base layer near to a p-type collector region. The short-lifetime region is an n-type one and doped more heavily than the n-type base layer. The short-lifetime region facilitates reducing the leakage current of the NPT-type IGBT.
The following documents describe related art.
1) Japanese Unexamined Patent Application Publication No. 2002-319676 (hereinafter referred to as “Patent Document 1”).
2) Japanese Unexamined Patent Application Publication No. 2006-080269 (hereinafter referred to as “Patent Document 2”).
3) Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2002-532885 (hereinafter referred to as “Patent Document 3”).
4) Japanese Unexamined Patent Application Publication No. Hei. 9 (1997)-326486 (hereinafter referred to as “Patent Document 4”).
5) Japanese Unexamined Patent Application Publication No. Hei. 9 (1997)-260662 (hereinafter referred to as “Patent Document 5”).
According the technique disclosed in the Patent Document 1, the reverse withstand voltage is lower than the forward withstand voltage. Generally, the NPT-type IGBT includes a p+-type body region in a base region for preventing latch-up breakdown from causing during the forward bias voltage application or during the turnoff of the device. The body region is doped much more heavily than the base region. The base region is doped more heavily than the drift region.
For reducing the turnoff loss, the collector region is doped more heavily than the drift region. The collector region is doped much more lightly than the body region. Due to the impurity concentration scheme, the depletion layer expanding from the collector region during the reverse bias voltage application is larger than the depletion layer expanding from the base region during the forward bias voltage application.
The width in the substrate depth direction of the base region not depleted (hereinafter referred to as the “neutral base region width”) during the reverse bias voltage application is the distance from the upper edge of the depletion layer expanding from the collector region to the base region. If described more in detail, the neutral base region width during the reverse bias voltage application is shorter than the neutral base region width during the forward bias voltage application, that is the distance from the lower edge of the depletion layer expanding from the base region to the collector region.
Due to the neutral base region width difference, the transport efficiency is larger during the reverse bias voltage application than during the forward bias voltage application. Therefore, the carrier amplification factor becomes much higher during the reverse bias voltage application than during the forward bias voltage application. Therefore, the reverse leakage current increases in association with the rise of the carrier amplification factor and the reverse withstand voltage lowers.
The technique disclosed in the Patent Document 3 causes the problems as described below. The relation between the height y from the substrate bottom plane and the electric field E is described in FIG. 13(b). Now the descriptions will be made with reference to FIGS. 13(a) and 13(b).
In the reverse blocking IGBT shown in FIG. 13(a), the electric field in the semiconductor substrate becomes high rapidly due to the disposition of shell region 201 and buffer region 202. During the forward bias voltage application for example (compare the solid lines in FIG. 13(b)), the electric field becomes high rapidly in region 211 in the vicinity of the boundary between base region 2 and shell region 201. During the reverse bias voltage application (cf. the broken lines in FIG. 13(b)), the electric field becomes high rapidly in region 212 in the vicinity of the boundary between collector region 10 and buffer region 202. Due to the rapid rise of the electric field, the forward and reverse withstand voltages lower in many cases. In other words, the forward and reverse withstand voltages to be obtained by the disposition of shell region 201 and buffer region 202 may not be realized actually.
It is known to the persons skilled in the art that the problems described above may be obviated by lowering the impurity concentration in the drift region. However, as the impurity concentration in the drift region is lowered, the depletion layer reaches buffer region 202 while the semiconductor device is operating, causing a reach-through phenomenon. Due to the reach-through phenomenon caused, oscillations are caused on the turnoff voltage waveform and the turnoff current waveform (hereinafter referred to collectively as the “turnoff waveforms”).
The reverse blocking IGBT exhibits the characteristics (reverse recovery characteristics) that make a high transient current flow when the reverse blocking IGBT is switched from the ON-state thereof to the reverse blocking state. Due to the reverse recovery characteristics, the reverse recovery voltage waveform and the reverse recovery current waveform (hereinafter referred to collectively as the “reverse recovery waveforms”) are liable to oscillations. In the case, in which the turnoff waveforms and the reverse recovery waveforms oscillate, the semiconductor device may be broken down, when noises are caused or when very large oscillations are caused on the voltage waveform.
In view of the foregoing, it is a first object of embodiments of the invention to obviate the problems described above. It is a second object of embodiments of the invention to provide a semiconductor device that facilitates improving the forward withstand voltage thereof. It is a third object of embodiments of the invention to provide a semiconductor device that facilitates improving the reverse withstand voltage thereof. It is a fourth object of embodiments of the invention to provide a semiconductor device that facilitates removing oscillations from the turnoff waveforms. It is a fifth object of embodiment of the invention to provide a semiconductor device that facilitates suppressing the oscillations on the reverse recovery waveforms.